• IEEE es la asociación profesional más grande del mundo dedicada al avance de la innovación tecnológica y excelencia en beneficio de la humanidad.
    Para conocer más, también visite www.ieee.org

Noticias y Actividades

Publicado el 27/10/2017

IEEE AR SSCS - Ciclo de charlas sobre Diseño Asincrónico de Alta Performance en Tecnología CMOS
30 y 31 de octubre y 1 de noviembre de 2017, en UTN BA, CABA

La Facultad Regional Buenos Aires de la Universidad Tecnológica Nacional (UTN BA), será sede del Programa de Disertantes Distinguidos (Distinguished Lecturerer Program) de la IEEE SSCS Solid State Circuits Society.
En este marco, contaremos con la presencia de dos investigadores de primera linea en el área de circuitos asincrónicos como lo son el Dr. Kenneth Stevens, de la Universidad de Utah (EE.UU.) y la Dra. Edith Beigné, de CEA-LETI (Grenoble, Francia).

Las charlas tendrán lugar los días lunes 30 y martes 31 de octubre y miércoles 1 de noviembre en la UTN - FRBA, de 18:00 a 20:00.
La inscripción es gratuita, pero deberán enviar previamente un correo indicando nombre y apellido y DNI a vlsi_lab@frba.utn.edu.ar

Esta cita corresponde a un nuevo encuentro dedicado en esta temática que hemos estado ofreciendo desde 2015.
Durante el presente ciclo de charlas, se abordarán las metodologías de Relative Timing, desarrollada por el Dr. Stevens y Delay Insensitive, campo de expertise de la Dra. Beigné.
En el caso de Relative Timing, se propone utilizar la paralelización como principal herramienta de diseño, mientras que por otro lado, la segunda propone realizar la sincronización entre distintos bloques del sistema independientemente de la temporización de la señales.
Estas metodologías de diseño permitirán a futuro, una reducción del 50% en el consumo de los circuitos integrados, con un aumento del 2x en la performance de los mismos.

* * * Edith Beigné, Bio:
Edith Beigné joined CEA-LETI, Grenoble, France, in 1998. Since 2009, she is a senior scientist in the digital and mixed-signal design lab where she researches low power and adaptive circuit techniques, exploiting asynchronous design and advanced technology nodes like FDSOI 28nm and 14nm for many different applications from high performance MPSoC to ultra-low power IoT applications. She is part of ISSCC TPC since 2014 and part of VLSI’ symposium since 2015.

Talk Abstract: “Asynchronous Design: a design and system solution for ultra low power Internet of Everything”
Asynchronous circuits have characteristics that differ significantly from those of synchronous circuits in terms of their power and robustness to variations. This talk will show how it is possible to exploit these characteristics to design ultra low power and robust circuits in the scope of the Internet-of-Everything (IoE) and also Globally Asynchronous and Locally Synchronous architectures. More specifically, the aims of the talk are to give fundamentals of asynchronous circuits design and to detail design methodologies with practical low power asynchronous circuits examples. At the end of the talk, attendees should be able to differentiate the usefulness of an asynchronous circuit compared to a synchronous one according to their application needs.

* * * Kenneth Stevens, Bio:
Ken Stevens received the B.A. degree in biology and the B.S. and M.S. degrees in computer science from the University of Utah, Salt Lake City, in 1982, 1982, and 1984, respectively, and the Ph.D. degree in computer science from the University of Calgary, Calgary, Calgary, Canada, in 1994. He is an Associate Professor with the University of Utah. Prior to this position, he worked with the Strategic CAD Lab, Intel, Hillsboro, OR, an Assistant Professor with the Air Force Institute of Technology, with Hewlett Packard Labs, and with Fairchild Labs, AI Research. His research interests include asynchronous circuits, VLSI, architecture and design, hardware synthesis and veri@257;cation, and timing analysis. Ken has degrees in Computer Science and Biology.

Talk Abstract: “Relative Timing”
To understand and implement low power, high performance digital systems that don't use a clock for sequencing events. Asynchronous design differs significantly from traditional clocked design practices that are currently being taught and used. The topics covered will include theoretical asynchronous design classifications and circuit families, hazards, communication channels, formal representation of sequential designs, synthesis, formal verification of sequential protocols, relative timing, synchronization and concurrency, protocol families and equivalence classes, asynchronous design classes, pipelining, and creating design wins through asynchronous design approaches.

 

Volver


Destacados


    

Descubra los beneficios
        de ser miembro IEEE

  • acceso a más de 200 e-books
  • IEEE memberNet
  • IEEE Job Site
  • y muchos beneficios más!

Para más información, haga clíck aquí


No deje de visitar los siguientes sitios IEEE:


Síganos en:

                   

         

       Política de privacidad IEEE